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AMD EPYC Embedded 9654P

AMD EPYC Embedded 9654P — Specifications and benchmarks. .

These specifications are supported by the linked sources. Core counts, clocks and memory capacities do not predict workload performance. Check benchmark versions, environments and sample counts.

Evidence review in progress · Search indexing deferred

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Power

ParameterValue and conditions
TDP
360 W
Source and conditions

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{
  "state": "known",
  "raw_label": "TDP",
  "raw_value": "360W",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "TDP",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}

Compute

ParameterValue and conditions
Base clock
2,400 MHz
Source and conditions

View source ↗

{
  "state": "known",
  "raw_label": "CPU Base Freq.",
  "raw_value": "2.4 GHz",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "CPU Base Freq.",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}
Max boost clock
3,700 MHz
Source and conditions

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{
  "state": "known",
  "raw_label": "CPU Max Freq.",
  "raw_value": "3.7 GHz",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "CPU Max Freq.",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}
CPU cores
96
Source and conditions

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{
  "state": "known",
  "raw_label": "# of CPU Cores",
  "raw_value": "96",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "# of CPU Cores",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}
threads
192
Source and conditions

View source ↗

{
  "state": "known",
  "raw_label": "# of Threads",
  "raw_value": "192",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "# of Threads",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}

Memory

ParameterValue and conditions
L3 cache
384 MB
Source and conditions

View source ↗

{
  "state": "known",
  "raw_label": "Total L3 Cache",
  "raw_value": "384 MB",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "Total L3 Cache",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}
Max supported memory (TB)
6 TB
Source and conditions

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{
  "state": "known",
  "raw_label": "Max. Memory",
  "raw_value": "6 TB",
  "qualifiers": {
    "capacity_scope": "per-socket",
    "evidence_checked_at": "2026-10-10T11:51:33.674259+00:00",
    "evidence_type": "manufacturer-specification",
    "family": "EPYC Embedded 9004 Series",
    "identity_match": "exact current catalog ID and manufacturer model/family evidence",
    "memory_population": "2DPC;256GB DIMMs;12channels",
    "memory_type": "DDR5",
    "not_board_slot_count": true,
    "not_installed_ram": true,
    "source_field": "Max. Memory",
    "source_revision": "Copyright2024 PID242924207-A; legacyLE-84301-00 11/22 footer",
    "source_row": 7,
    "source_section": "PDF page1 capacity passage;page3 exact models",
    "source_sha256": "8a904d6bba492b8be02ec66518e4135eef06b622abe942696b951e7365e1dac8"
  },
  "document_id": "reaudit-epyc-embedded-9004-memory-8a904d6bba492b8b"
}
Memory type
DDR5
Source and conditions

View source ↗

{
  "state": "known",
  "raw_label": "Memory Type",
  "raw_value": "DDR5",
  "qualifiers": {
    "release_evidence": "manufacturer-listed-date-unknown",
    "source_field": "Memory Type",
    "source_product_url": "",
    "source_row": 52
  },
  "document_id": "amd-embedded-table-29b3e28c58f1e349"
}

Public benchmarks

Compare results with matching versions, scenes, settings and statistics. A run count of 0 identifies an aggregate or reported value, not a newly measured run.

No comparable public scores are available. This does not mean a score of zero or poor performance.

Sources

Source terms and retrieval dates are listed below. Published values and conditions may change.